Conventionally, there is known a liquid crystal display device including a display unit that includes a plurality of source bus lines (video signal lines) and a plurality of gate bus lines (scanning signal lines). For such a liquid crystal display device, conventionally, a gate driver (scanning signal line drive circuit) for driving the gate bus lines is often mounted, as an integrated circuit (IC) chip, on the periphery of a substrate forming a liquid crystal panel. However, in recent years, the formation of the gate driver directly on a TFT substrate which is one of two glass substrates forming the liquid crystal panel has been gradually increasing. Such a gate driver is called “monolithic gate driver”, etc.
In the liquid crystal display device, a pixel formation portion that forms a pixel is provided at an intersection of a source bus line and a gate bus line. Each pixel formation portion includes a thin film transistor which is a switching element connected at its gate terminal to a gate bus line passing through a corresponding intersection and connected at its source terminal to a source bus line passing through the intersection; a pixel capacitance for holding a pixel voltage value; and the like. The liquid crystal display device is also provided with the above-described gate driver and a source driver (video signal line drive circuit) for driving the source bus lines.
A video signal representing a pixel voltage value is transmitted by a source bus line. However, each source bus line cannot transmit video signals at a time (simultaneously), the video signals representing pixel voltage values for a plurality of rows. Hence, writing (charging) of video signals to the pixel capacitances in the plurality of pixel formation portions provided in the display unit is sequentially performed row by row. Hence, the gate driver is composed of a shift register including a plurality of stages, so that the plurality of gate bus lines can be sequentially selected for a predetermined period. Then, by sequentially outputting active scanning signals from the respective stages of the shift register, writing of video signals to the pixel capacitances is sequentially performed row by row as described above. Note that, in this specification, a circuit that forms each stage of the shift register is referred to as “unit circuit”.
FIG. 43 is a circuit diagram, of a conventional unit circuit having the simplest configuration. The unit circuit includes four thin film transistors T81 to T84 and one capacitor CAP. In addition, the unit circuit has one output terminal 80 and four input terminals 81 to 84, in addition to input terminals for a low-level direct-current power supply potential VSS. A gate terminal of the thin film transistor T81, a source terminal of the thin film transistor T83, and a drain terminal of the thin film transistor T84 are connected to each other. A region in which they are connected to each other is referred to as “output control node”. The output control node is denoted by reference character NA. Note that in general one of a drain and a source with a higher potential is called a drain, but in the description of this specification, since one is defined as a drain and the other as a source, a source potential may be higher than a drain potential. In addition, the potential magnitude of the low-level direct-current power supply potential VSS is referred to as “VSS potential” for convenience sake.
An output signal G is outputted from the output terminal 80. The output signal G is provided as a scanning signal to a gate bus line connected to this unit circuit, and provided as a control signal to a unit circuit of the previous stage and a unit circuit of the subsequent stage. A clock signal CKa is provided to the input terminal 81. A clock signal CKb is provided to the input terminal 82. Note that the clock signal CKa and the clock signal CKb are shifted in phase by 180 degrees relative to each other. An output signal G outputted from the unit circuit of the previous stage is provided as a set signal S to the input terminal 83. An output signal G outputted from the unit circuit of the subsequent stage is provided as a reset signal R to the input terminal 84. Note that in the following the “unit circuit of the previous stage” may be simply abbreviated as “previous stage”, and the “unit circuit of the subsequent stage” may be simply abbreviated as “subsequent stage”.
The thin film transistor T81 is connected at its gate terminal to the output control node NA, connected at its drain terminal to the input terminal 81, and connected at its source terminal to the output terminal 80. The thin film transistor T82 is connected at its gate terminal to the input terminal 82, connected at its drain terminal to the output terminal 80, and connected at its source terminal to am input terminal for a direct-current power supply potential VSS. The thin film transistor T83 is connected at its gate and drain terminals to the input terminal 83 (i.e., diode-connected) and connected at its source terminal to the output control node NA. The thin film transistor T84 is connected at its gate terminal to the input terminal 84, connected at its drain terminal to the output control node NA, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The capacitor CAP is connected at its one end to the output control node NA and connected at its other end to the output terminal 80.
Next, with reference to FIG. 44, the operation of the unit circuit of the configuration shown in FIG. 43 will be described. Note that in the following, for each unit circuit, a period during which operation is performed to write (charge) to pixel capacitances in pixel formation portions connected to a corresponding gate bus line is referred to as “write operation period”. Note also that a period other than the write operation period is referred to as “normal operation period”. In FIG. 44, a period from time point t80 to time point t82 is a write operation period, and a period before time point t80 and a period after time point t82 are normal operation periods.
First, operation performed during the write operation period will be described. At time point t80, a pulse of the set signal S is provided to the input terminal 83. Since the thin film transistor T83 is diode-connected as shown in FIG. 43, by the pulse of the set signal S, the thin film, transistor T83 goes into an on state and the capacitor CAP is charged. By this, the potential of the output control node NA increases and the thin film transistor T81 goes into an on state. Here, during a period from time point t80 to time point t81, the clock signal CKa is at a low level. Hence, during this period, the output signal G is maintained at a low level. In addition, during the period from time point t80 to time point t81, since the reset signal R is at a low level, the thin film transistor T84 is maintained in an off state. Hence, the potential of the output control node NA does not decrease during this period.
At time point t81, the clock signal CKa changes from the low level to a high level. At this time, since the thin film transistor T81 is in the on state, the potential of the output terminal 80 increases with an increase in the potential of the input terminal 81. Here, since the capacitor CAP is provided between the output control node NA and the output terminal 80 as shown in FIG. 43, the potential of the output control node NA also increases with the increase in the potential of the output terminal 80 (the output control node NA is bootstrapped). As a result, a large voltage is applied to the gate terminal of the thin film transistor T81, and the potential of the output signal G increases to a high-level potential of the clock signal CKa. By this, the gate bus line connected to the output terminal 80 of this unit circuit goes into a selected state. Note that during a period from time point t81 to time point t82, the clock signal CKb is at a low level. Hence, since the thin film transistor T82 is maintained in an off state, the potential of the output signal G does not decrease during this period.
At time point t82, the clock signal CKa changes from the high level to a low level. By this, the potential of the output terminal 80 decreases with a decrease in the potential of the input terminal 81, and the potential of the output control node NA also decreases through the capacitor CAP. In addition, at time point t82, a pulse of the reset signal R is provided to the input terminal 84. By this, the thin film transistor T84 goes into an on state. As a result, the potential of the output control node NA changes from the high level to a low level. In addition, at time point t82, the clock signal CKb changes from the low level to a high level. By this, the thin film transistor T82 goes into an on state. As a result, the potential of the output signal G goes to a low level.
In the above-described manner, during the second half-period of the write operation period, an active scanning signal is provided to the gate bus line corresponding to this unit circuit. An output signal G outputted from a unit circuit of any stage is provided as a set signal S to the subsequent stage. By this, the plurality of gate bus lines provided to the liquid crystal display device sequentially go into a selected state, and writing to the pixel capacitances is performed row by row.
However, according to the above-described configuration, during the normal operation period, the potential of the output signal G (scanning signal) which is supposed to be fixed at a low level may fluctuate due to noise caused by the clock signal CKa, which will be described below. A parasitic capacitance is formed between the electrodes of a thin film transistor in a unit circuit that forms the shift register. Therefore, in the configuration shown in FIG. 43, a parasitic capacitance is formed between the gate and drain of the thin film transistor T81 and also between the gate and source of the thin film transistor T81. Hence, when the clock signal CKa changes from a low level to a nigh level, the gate potential of the thin film transistor T81 increases through the parasitic capacitance. That is, despite the fact that the potential of the output control node NA is supposed to be fixed at a low level, the potential of the output control node NA increases somewhat (the potential of the output control node NA floats). By this, a leakage current flows through the thin film transistor T81 and accordingly the potential of the output signal G fluctuates. As can be grasped from FIG. 44, the clock signal CKa changes from a low level to a high level in a predetermined cycle throughout an operation period of the liquid crystal display device. Therefore, the potential of the output signal G (scanning signal) fluctuates in the predetermined cycle during the normal operation period. As a result, abnormal operation or an increase in power consumption is caused.
In view of this, in general, the unit circuit is provided with a circuit for maintaining the potential of the output control node NA at a low level throughout the normal operation period (hereinafter, referred to as “output control node stabilization portion”). FIG. 45 is a diagram schematically showing a configuration of a unit circuit having the output control node stabilization portion. As shown in FIG. 45, the unit circuit is provided with an output control node stabilization portion 950, in addition to a buffer 910, a scanning signal stabilization portion 920, an output control node setting portion 930, and an output control node resetting portion 940. Note that the thin film transistor T81, the thin film transistor T82, the thin film transistor T83, and the thin film transistor T84 of FIG. 43 correspond to the buffer 910, the scanning signal stabilization portion 920, the output control node setting portion 930, and the output control node resetting portion 940 of FIG. 45, respectively.
A specific configuration of a conventional unit circuit having an output control node stabilization portion is disclosed in, for example, WO 2010/067641 A. FIG. 46 is a circuit diagram showing a configuration of a unit circuit disclosed in WO 2010/067641 A. The unit circuit shown in FIG. 46 includes 10 thin film transistors T91 to T100 and one capacitor CAP. In addition, the unit circuit has one output terminal 90 and six input terminals 91 to 96. A gate terminal of the thin film, transistor T91, a drain terminal of the thin film transistor T92, a source terminal of the thin film transistor T95, a gate terminal of the thin film transistor T96, and a drain terminal of the thin film transistor T97 are connected to each other through an output control node NA. A gate terminal of the thin film transistor T92, a source terminal of the thin film transistor T93, a drain terminal of the thin film transistor T94, a drain terminal of the thin film transistor T96, and a gate terminal of the thin film transistor T100 are connected to each other. A region in which they are connected to each other is referred to as “stabilization node”. The stabilization node is denoted by reference character NB.
The thin film transistor T91 is connected at its gate terminal to the output control node NA, connected at its drain terminal to the input terminal 91, and connected at its source terminal to the output terminal 90. The thin film transistor T92 is connected at its gate terminal to the stabilization node NB, connected at its drain terminal to the output control node NA, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The thin film transistor T93 is connected at its gate and drain terminals to the input terminal 93 (i.e., diode-connected) and connected at its source terminal to the stabilization node NB. The thin film transistor T94 is connected at its gate terminal to the input terminal 94, connected at its drain terminal to the stabilization node NB, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The thin film transistor T95 is connected at its gate and drain terminals to the input terminal 95 (i.e., diode-connected) and connected at its source terminal to the output control node NA. The thin film transistor T96 is connected at its gate terminal to the output control node NA, connected at its drain terminal to the stabilization node NB, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The thin film transistor T97 is connected at its gate terminal to the input terminal 96, connected at its drain terminal to the output control node NA, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The thin film transistor T98 is connected at its gate terminal to the input terminal 96, connected at its drain terminal to the output terminal 90, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The thin film transistor T99 is connected at its gate terminal to the input terminal 92, connected at its drain terminal to the output terminal 90, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The thin film transistor T100 is connected at its gate terminal to the stabilization node NB, connected at its drain terminal to the output terminal 90, and connected at its source terminal to an input terminal for a direct-current power supply potential VSS. The capacitor CAP is connected at its one end to the output control node NA and connected at its other end to the output terminal 90. In a configuration such as that described above, the above-described output control node stabilization portion 950 is implemented by the thin film transistors T92, T93, T94, and T96.
FIG. 47 is a signal waveform diagram for describing the operation of the unit circuit of the configuration shown in FIG. 46. As can be grasped from FIG. 47, the unit circuit operates based on 4-phase clock signals (a clock signal CKa, a clock signal CKb, a clock signal CKc, and a clock signal CKd) which are shifted in phase by 90 degrees relative to each other. In FIG. 47, attention is focused on a normal operation period. During the normal operation period, since the potential of the output control node NA is maintained at a low level, the thin film transistor T96 is maintained in an off state. In addition, during a period during which the clock signal CKc is at a high level and the clock signal CKd is at a low level, the thin film transistor T93 is in an on state and the thin film transistor T94 is in an off state. In addition, during a period during which the clock signal CKc is at a low level and the clock signal CKa is at a high level, the thin film transistor T93 is in an off state and the thin film transistor T94 is in an on state. By the above, as shown in FIG. 47, during the normal operation period, the potential of the stabilization node NB goes to a high level every predetermined period. By this, during the normal operation period, the thin film transistor T92 goes into an on state every predetermined period, and the potential of the output control node NA is drawn to the VSS potential. In the above-described manner, the potential of the output control node NA is prevented from floating during the normal operation period, implementing a monolithic gate driver that does not cause abnormal operation. Note that the thin film transistor T96 is provided to prevent the potential of the stabilization node NB from going to a high level during the write operation period.